1. Field of the Invention
Embodiments of the invention relate to the field of device manufacturing. More particularly, the present invention relates to a method, system and structure for controlling roughness and critical dimension in patterned resist features.
2. Discussion of Related Art
Optical lithography is often used in manufacturing electronic devices. It is a process by which a substrate is patterned so that circuits may be formed on the substrate according to the pattern. Referring to FIGS. 1a-1e, there are shown simplified illustrations of an optical lithographic process. Generally, the substrate 112 is coated with photo-curable, polymeric photoresist 114 as shown in FIG. 1a. Thereafter, a mask 142 having a desired aperture pattern is disposed between the substrate 112 and a light source (not shown). The light 10 from the light source is illuminated onto the substrate 112 via the aperture of the mask 142, and the light transmitted through the mask's aperture (or the image of the pattern) is projected onto the photoresist 114. A portion of the photoresist 114a is exposed to the light 10 and cured, whereas the rest of the photoresist 114b remains uncured as illustrated in FIG. 1b. As a result, an image of the mask's aperture is formed by the cured portion of the photoresist 114a. 
As illustrated in FIG. 1c, the uncured portion of the photoresist 114b is stripped, and a three dimensional (3D) photoresist relief feature 114a corresponding to the mask's aperture pattern may remain on the substrate 112. Thereafter, the substrate is etched, and trenches 116 corresponding to the negative image of the mask's aperture pattern may form (FIG. 1d). After the remaining photoresist 114b is removed, a patterned substrate 112 is formed as illustrated in FIG. 1e. If a metallic layer is deposited on the trenches, a circuit having a desired pattern may be formed on the substrate 112.
Although optical lithography is an efficient process with high throughput, the process is not without disadvantages. One disadvantage may include line width roughness (LWR) or line edge roughness (LER). As known in the art, LWR is excessive variations in the width of the photoresist relief feature formed after uncured portions of the photoresist 114b is stripped from the substrate. If the variations occur on the side surface of the photoresist relief or feature the variation is known as LER. The roughness or variations due to LWR or LER may be disadvantageous as the variation may be transferred onto the trenches during etch and ultimately to the circuit. The variations become more significant with a decrease in feature size of the photoresist relief or trenches. For 32 nm devices variations of 4 nm or larger have been observed. Because the geometrical shape of a patterned resist feature, including line roughness effects such as LWR and LER, is transferred from a resist layer to an underlying permanent layer of a device during patterning of the underlying layer, LWR and LER can limit the ability to form devices of acceptable quality for dimensions below about 100 nm. Such variations may lead to non-uniform circuits and ultimately device degradation or failure. In addition, depending on design criteria, device performance may be impacted more by either one of short, medium, or long range roughness.
Several approaches have been attempted to address LWR and LER effects (the combination of either LWR, LER or both LWR and LER may be referred to collectively hereinafter as “line roughness”). One technique that shows promise for reducing line roughness is ion beam smoothening in which ions are directed over a range of angles towards patterned photoresist relief features. This technique has met with success in modifying line roughness in narrow photoresist relief features in which the critical dimension is less than about 100 nm. In a typical ion beam smoothening process using ions directed over a range of angles on the patterned photoresist, the LWR/LER can be reduced up to about 50%. However, the critical dimension (CD) may also decrease by up to about 10 nm after an ion beam smoothening process is performed, which may represent an unacceptably large decrease depending on desired device characteristics.
Increasing the power of a plasma source used during an ion beam smoothening process has been observed to lessen or eliminate the reduction in CD, but the increased power has also been observed to be less effective in reducing line roughness [For instance, performing an ion beam smoothening process at 300 W may result in a ˜25% reduction in LWR, but may also yield a ˜20% reduction in CD. At 500 W power, the loss of CD may be close to zero, however, the reduction in LWR may be only about 15%, which may not meet designer specifications.] Thus, the present day ion beam smoothening process presents a tradeoff between improved roughness versus loss of critical dimension. In view of the foregoing, it will be appreciated that there is a need to improve photoresist processing techniques for technologies requiring very small feature sizes, such as sub-100 nm CD devices.